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Workcraft v3.2.4 (2019-07-31)

Usability improvements

  • Support for basic operations with hierarchical design using Circuit and STG models:
    • Refinement models as a property of circuit components and STGs
    • Navigation through refinement models via popup menu or double-clicking
    • Export of a circuit with refined components into a hierarchical Verilog netlist
    • Import of hierarchical Verilog netlist as a circuit with refinement models for its components (the user can select the top module)

Model and tool plugins

  • Digital Circuit plugin
    • Improved support for “substitution rules” on import/export of Verilog netlists. Now separate conversion files can be specified for import and export, with possibility to invert the rules (e.g. when the same conversion file is used both for import an export)
    • Improvement of loop breaking tool:
      • Support for TBUF and TINV loop breaking gates
      • The button for write SDC set_disabled_timing constraints becomes enabled only when there are input pins tagged as path breaker.
      • Possibility to extend existing scan chain with new testable elements
  • Signal Transition Graph plugin
    • Add an extra row in the violation report for N-way conformation (Table and List styles) that characterises the problematic output.
    • Handling the violation of place promised capacity during simulation. A warning dialog box appears once for each place whose promised capacity is violated.
  • Initial integration of MSFSM backend for synthesis of Multiple Synchronised FSMs
    • Convert Petri net to multiple synchronised FSMs (Convert→Synchronised FSMs [MSFSM])
    • Convert STG to multiple synchronised FSTs (Convert→Synchronised FSTs [MSFSM])
    • Settings for configuration of MSFSM backend (Edit→Preferences…→External tools→MSFSM)
    • Note that MSFSM backend is still under development and is bundled with Workcraft yet. Its Linux binaries and conversion examples are available in this repo: To activate the tool put the msfsm_tools binary in tools/MSFSM directory and enable it via Activate MSFSM backend (experimental) – requires restart setting.

Fixes and technical stuff

  • Bugfix for visualisation of circuit pins in Cycle analyser tool (all input pins after a fork were highlighted magenta, even if not all of them were on a cycle)
  • Bugfix for conversion of a simulation trace into DTD (the first level was missing if initial state was high)
  • Bugfix for import of Verilog netlist with disconnected pins
  • Adaptation of unit tests so they can pass on Windows
  • Updated offline help and tutorials

Previous versions