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changelog:v3.0.9

Workcraft v3.0.9 (2016-04-10)

Usability improvements

  • The transformation tools that are specific to a particular type of node are accessible by a right-click in its popup menu.
  • Less intrusive light grid is used by default. The old-style grid can be restored in global settings (Edit→Preferences… menu) by modifying the Editor→Use light grid option.
  • Fan and fold-ruler modes for continuous connection. Default is fold-ruler mode of continuous connection – the last node of the previous arc becomes the first node of the next arc. In circuit plugin fan mode works better – the first node is the same for all arcs.
  • Add straighten connection tool into popup menu.
  • Items Report a bug at GitHub and Contact developers by e-mail are added to the Help menu.
  • Configurable visibility of the hint messages at the bottom of the editor via Editor→Show hints option in global settings.

Model and tool plugins

  • Digital Circuit plugin
    • Circuit initialisation analyser (the last button in the Editor tools panel) to help identifying the gates that cannot be correctly initialised via the primary inputs and require explicit reset circuitry. A separate tutorial will be created to illustrate the usage of this tool.
    • Extra checks for circuit environment STG. An STG that has not been saved in a file cannot be set as a circuit environment – an error message is produced on such attempt. Also a warning is issued in case of a modified STG being set as the circuit environment. Circuit conformation is denied without environment STG.
    • Names of zero-delay components are hidden by default. These names are usually irrelevant as they do not have associated signals for simulation or verification traces. Their visibility can be configured in Digital Circuit→Show names of zero-delay components option of Edit→Preferences… menu.
    • Configurable suffixes for STG signals (signal_HIGH and signal_LOW by default).
    • Force rendering of generalised C-elements as BOX.
    • Transformation tool for contraction of circuit joint.
    • Transformation tool for contraction of single-input circuit components.
    • Transformation tool for splitting wire joint points.
    • Transformation tool for toggling inversion of the gate pins.
    • Position new pins in the middle of BOX components, so the existing pin positions are preserved.
    • Improved GenLib parser that accepts keywords as module IDs (e.g. INV).
    • Circuit contact properties are filtered by IO type: Init to one, Forced init, Set function, Reset function are only visible on the driver pins (primary inputs and gate outputs).
    • Export unmapped gates into Verilog as assign statements (if set or reset functions are specified).
  • Signal Transition Graph plugin
    • Names of places with proxies are always visible
    • Implicit place position in the middle of arc.
    • Verification of input properness property (inputs are not triggered by internal signals and are not disabled by non-input signals).
    • Optimisation of Reach expressions for output persistency.
    • Simpler geometry of new arcs after trivial contraction of transitions (e.g. with single node in preset and in postset).
    • Transformation tool for dummy insertion into an arc.
  • Conditional Partial Order Graph plugin
    • Improved interface to PGMiner backend tool.
    • Event log file is used for all process-mining cases, reducing the number of temporary files used.
  • Structured Occurrence Net plugin
    • BFS node estimation facility.
    • Add undo/redo in time property setter.
    • A tutorial on using SONs for investigation of crime and accident scenes.
  • xMAS Circuit plugin
    • Correction of the synchroniser model and sync query.

Fixes and technical stuff

  • Termination of external processes (backend tools) is explicitly synchronised with their stdout and stderr streams. In rare situations the lack of synchronisation caused incorrect interpretation of results produced by the backend tools, e.g. in CSC check (Verification→Complete State Coding (all cores) [MPSat] menu of STG plugin).
  • JavaCC parser files are generated by the build script.
  • New distribution format – all Workcraft core classes are packaged in workcraft.jar while each plugin is put in its own jar file under plugins directory.
  • The whole codebase is reformatted for consistent style (a subset of Checkstyle requirements). New code is automatically checked to satisfy the same style.
  • Unit tests are re-arranged into core tests and plugin tests. Coverage is calculated.
  • Unified handling of temporary files in FileUtils class. The temporary file prefix is extended to the minimum length (3 symbols) if necessary. Special symbols are replaced by underscore.
  • Convert model title to C-style before STG export. This is necessary as special symbols in STG model name upset Petrify backend tool.
  • UnfoldingTools are updated. In particular logic decomposition and technology mapping in MPSat is sped up significantly.
  • PGMiner tool (process mining) is updated
  • VXM tool (xMAX verification) is updated.
  • Command line parameters -version and -help are added.
  • Hierarchy separator is no longer configurable as it is prone to errors. It is safer to keep it fixed to a forward slash.
  • Change indent-number XML option to indent-amount.