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changelog:v3.1.0

Workcraft v3.1.0 (2016-05-29)

Usability improvements

  • First release with OS X support!
  • Better support for high DPI displays. A configurable Visual→Base font size (points) value is used to scale the GUI elements.
  • Signal related settings (shared among FST, STG, Circuit, and DTD) are moved to Common preferences.
  • Improved handling of backend tool failure – a more detailed message is output to the user.

Model and tool plugins

  • Digital Circuit plugin
    • Separate setting Open synthesis results as Digital Circuit for Petrify and MPSat backends.
    • Check for circuit integrity before component contraction.
  • Signal Transition Graph plugin
    • New verification property Delay insensitive interface (without dummies) [MPSat].
    • Tool for mirroring polarity of STG signal transitions.
    • Forbid several connections between STG transitions (this leads to implicit places with ambiguous names and contradicts definition of STGs).
    • Non-ASCII characters are forbidden in Reach expression editor of custom verification properties.
    • Improvements for MPSat custom verification dialog.
    • Remove isolated marked places before calling Petrify, as such places are redundant but upset Petrify .g parser.
    • Warning on increase of place capacity during simulation.
    • Simulation tool is moved from Petri nets and STG plugins into Workcraft core.
  • Graph plugin
    • Extended by vertex labelling function to serve as a basis for timing diagrams model.
    • Converter from Graph to Petri net.
    • Reuse of Petri net simulation engine for Graphs.
    • A tool for identifying unreachable vertices.
  • Digital Timing Diagram plugin
    • A new plugin to support visualisation and editing of timing diagrams.
    • Using connection tool to order signal events.
    • Movement of signal waveforms and signal edges is restricted by causality arcs.
    • Generating Edge and Pulse patterns of timing diagrams by clicking on the signal name and signal level respectively.
    • Converter from STG and Circuit simulation traces into timing diagram. It is activated by pressing the Generate trace diagram button in the simulation tool.
    • The order of signals in the timing diagram can be rearranged by drag-and-drop of the Signal state table rows in the simulation tool.
    • Configurable visibility and color of signals waveforms in the Signal state table.
  • Conditional Partial Order Graph plugin
    • CPOG algebra tools are moved to a dedicated Algebra menu.
    • Code for evaluation, rendering and minimisation of Boolean formulas is moved from CPOG plugin into Workcraft core.
    • Optimisation to enable rendering vertices as labels even in larger CPOG models.

Fixes and technical stuff

  • All backend tools are built for OS X.
  • Standard OS-specific configuration directory.
  • Clean up of the source code to comply with more Checkstyle and PMD rules.
  • Trailing directory separator is made explicit in path variables of workcraft.bat – some versions of Windows require this.
  • Refactoring for consistent plugin naming.