changelog:v3.3.7
Workcraft v3.3.7 (2022-03-25)
Usability improvements
Add possibility to pan editor view in full viewport steps via Ctrl+Shift+←, ↑, →, ↓
Prevent drag-and-drop of graph elements while selecting with Ctrl/Shift
Digital Circuit plugin
For better visibility, use bold contact outlines for enabled signals in circuit simulation
Improve compatibility diagnostics between circuit component and its refinement model
Add means to quickly locate circuit components via model-level Property editor
Extend support for importing Verilog with buses
Improve import/export of Verilog with disconnected pins and empty modules
Recognise WAIT and WAIT0 components as arbitration primitives on Verilog import
Wider default positioning for component pins
Access refinement model of Circuit component from JavaScript using this functions:
setCircuitComponentRefinement(circuitWork, componentRef, refinementPath)
getCircuitComponentRefinement(circuitWork, componentRef)
Fixes and technical stuff
Update of the build system to Gradle v7.4, PMD v6.42, Checkstyle v9.3
Bundle statically linked Graphviz DOT Linux binaries with the distribution
Use windows-2019
and macos-10.15
instead of latest
in GitHub Actions
Update Spot ltl2tgba backend to v2.10.2
Save Workcraft compatibility version in meta data to prevent multiple warnings when opening work files created by newer version of Workcraft
Fix tracking of internal-to-dummy renaming
Fix filtering of nodes with custom hit function
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