changelog:v3.0.6
Workcraft v3.0.6 (2015-11-02)
Usability improvements
Frequently used Tools→Conversion menu is promoted to the main menu bar.
Support for read-arcs in Petri net and
STG plugins. Tools for conversion between read-arcs and pairs of producing/consuming arcs.
Support for replica places in Petri net and
STG plugin. A replica place is created if
Shift is held while creating a connection to/from a place.
In simulation mode of Petri nets and STGs the consuming arcs from marked places are highlighted.
A generic tool for merging selected nodes of the same type. This tool is accessible under
Transformations menu as follows:
Merge selected vertices for Graph model,
Merge selected states for
FSM and
FST models,
Merge selected places for Petri net and
STG models, and
Merge selected components for Dataflow Structures.
User documentation is added for Dataflow Structures plugin.
Digital Circuit plugin
Automated conversion of MPSat synthesis results into a Digital Circuit work.
Complex gate synthesis – the self-dependencies of signals are interpreted as self-loops on combinational gates.
Generalised C-element synthesis – the self-dependencies result in sequential gates.
Standard C-element synthesis – the set and reset functions are extracted from the assign statement.
Technology mapping - zero delay inverters are taken into account.
Verilog parser is extended to read assign statements and interpret them as unmapped gates.
Improved handling of self-loops in circuit layout tool.
Support for zero delay gates – visualised as a gate with a pass-through dotted wire when its Zero delay property is true. Note that only buffers and inverters can be set as zero delay. Also zero delay gates cannot be connected to other zero delay gates or primary outputs. A suggested use for zero delay buffers and inverters is as follows:
Zero delay inverters mimic input bubbles on the gates and should be placed close to those gates. The information about zero delay inverters is read from technology mapping results of Petrify and MPSat.
Buffers can be used to test the need for isochronic fork timing assumptions. Insert a buffer in each branch of a fork. If it causes a hazard, then tag the fork buffers as zero delay one by one, until a hazard-free operation is achieved. The remaining buffers will suggest the timing assumptions associated with the fork.
Fixes and technical stuff
MpsatPlugin is split into 4 plugins: MpsatVerificationPlugin, MpsatSynthesisPlugin, PunfPlugin and PcomPlugin.
MPSat is updated (backend tool for synthesis and verification of speed-independent circuits).
PGMiner is updated (backend tool for process mining).
ScEnco is updated (backend tool for scenario encoding of CPOGs).
VXM is included in the distribution (a backend tool for verification of xMAS circuits).
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