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changelog:v3.1.2

Workcraft v3.1.2 (2016-09-21)

Usability improvements

  • Improved report and extended violation traces for output persistency and conformation (both for circuits and STGs).
    • For output persistency a transition that disables a non-persistent signal is appended to the solution trace.
    • For conformation a transition that is not expected by the environment is appended.
    • The name of problematic signal is also reported in the Verification results window and in the Output tab.
  • Generate waveform for a combined Trace/Branch sequence of events.
  • Close CMD window after running workcraft.bat in Windows.
  • Activate text entry on creation of Comment node
  • Esc key can be used for switching back to the selection tool.

Model and tool plugins

  • Digital Circuit plugin
    • Improve bubble toggling on circuit contact.
    • Enhance user experience in circuit simulation.
    • Extend properties of single-output gates with Set function, Reset function, Init to one, and Forced init properties of their output contact.
    • To avoid confusion the term hazard is replaced by non-persistency (e.g. Hazard-freeOutput persistent, Hazardous signalNon-persistent signal).
    • Support for CONST0/CONST1 keywords in GenLib file (to specify TIEHI/TIELO type of gates).
  • Signal Transition Graph plugin
    • Interface to Concepts backend tool for specification of STGs using Concepts. It is available under Conversion→Translate concepts menu. Also available via File→Import… menu.
    • Remove redundant anchors after transition contraction.

Fixes and technical stuff

  • Fix for PNConf generation in Xmas plugin.
  • Pass vxm temporary directory as a working directory to fix OSX version of xMAS plugin.
  • Support for assign statements in new version of Petrify (to be released later).
  • Petrify is used with -mc option for stdC synthesis now. We came to a conclusion that -gcm option is impractical (less interesting than both -mc and -gc) and removed it from the Synthesis menu.
  • Updated UnfoldingTools
    • In the stdC mode, when a signal implementation is degraded, MPSAT generates a CG one.
    • When a set or reset cover in stdC is a single literal, monotonicity constraint is not required and MPSAT now optimizes the implementation.
    • Better support of constants at synthesis and Verilog export.
  • Support for new version of Petrify (not included in the distribution as currently only Linux binary is available).