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changelog:v3.2.0

Workcraft v3.2.0 (2018-06-30)

Usability improvements

  • New tutorial on logic decomposition and technology mapping.
  • New tutorial on verification and synthesis of hierarchical designs, including N-way conformation.
  • Dot layout can be configured left-to-right, top-to-bottom, right-to-left, or bottom-to-top. It is left-to-right by default. This can be changed in Layout→Dot→Direction of lay out setting that is accessible via Edit→Preferences… menu.

Model and tool plugins

  • Digital Circuit plugin
    • Improved Verilog parser: support for port ranges (i.e. busses) and multi-line comments
    • Tuned parameters of the circuit automatic layout to prevent touching of wire corners. Support for wire routing in hierarchical circuits (with groups and pages).
    • Error message if the initial state of interface signals differs in circuit and its environment STG. This check is performed before any verification command that uses environment STG.
    • Improved log messages and small corrections for trace projection in circuit verification commands.
    • New circuit transformation commands:
      • Splitting multi-level complex gates (Transformations→Split multi-level gates (selected or all) in the main menu or Split multi-level gate in a gate popup menu). The decorations and initial state of the split gates are derived from the original multi-level gate.
      • Propagating inversion through the gate using De Morgan law (Transformations→Propagate inversion through gates (selected or all) in the main menu or Propagate inversion through gate in a gate popup menu).
      • Toggling zero delay attribute (Transformations→Toggle zero delay of selected buffers and inverters in the main menu or Toggle zero delay in a gate popup menu.)
  • Signal Transition Graph plugin
    • First version of plugin for ATACS backend. This supports complex gate, generalised C-element, and standard C-element synthesis styles via corresponding Synthesis→… [ATACS] menu items.
    • Warning if Petrify technology mapping did not manage to map some of the signals.
    • Information on number and type of signals in the statistics report accessible via Tools→Statistics→Signal Transition Graph menu.
    • Improved log messages for N-way conformation.

Fixes and technical stuff

  • Simple anonymous classes (e.g. implementations of Runner, Func, ActionListener interfacers) are converted to Java 8 lambdas.
  • Updated JavaCC parser generator to v1.8, Checkstyle to v8.1, Jacoco to v0.8.1.
  • Extended Decoration interface to enable drawing on model canvas from external tools.
  • Enable registration of Tools directly from Module declaration.
  • Refactoring Boolean formula classes and utilities. Support for decomposition of Boolean expressions.
  • Build and test support for Kotlin language.
  • Full support of InteliJ IDEA for development of Workcraft:
    • Automatic generation of project files from Gradle build script.
    • Split test directories into test-src and test-res.
    • Detailed instructions for IDEA integration in developer documents.