-noconfig – do not read global config file and do not overwrite it on Workcraft exit

-noconfig-load – do not read global config file and use default values for all Workcraft settings

-noconfig-save – do not overwrite global config file on Workcraft exit

-config:CONFIG – use the specified CONFIG file as a global config file instead of the default one

-config-add:CONFIG – read local CONFIG file to override the settings that have been read from global config file or the default settings

Two sets of rules for converting sequential gates into their resettable init-low and init-high counterparts. Each set is a comma-separated list of original_gate->replacement_gate(init_pin), e.g. C2->C2_R(rst), NC2->NC2_R(rst), MUTEX->MUTEX_R(rst) and C2->C2_S(set), NC2->NC2_S(set). Only those gates that have a conversion rule would be explicitly reset.

Improve Scan insertion flexibility to handle multiple testing scenarios

Support for circuit initialisation using Scan

Exclude zero-delay gates from verification of circuit initialisation

Support for net range and bus concatenation on Verilog import

Extraction of set/reset functions from GenLib specification of latches

Check interface consistency for port/pin names and their initial states on component squashing

Provide more details in the verification output for circuit initialisation and cycle breaking

Improve circuit initialisation analyses and cycle analyser tools

Statistics command to report refinement dependencies

Enable visual feedback on refinement model status

Place components of large imported circuit, but do not attempt to route wires