changelog:v3.3.9
Workcraft v3.3.9 (2022-12-20)
Usability improvements
Digital Circuit plugin
Highlight circuit components in the
Property editor based on their refinement type (
none,
STG,
circuit,
error)
Improve random layout of Circuit model
Enable repacking circuit components to accommodate their pin names
Command to update component (name, input/output pins) from its refinement model
Make unconnected component pins more visible
Check initial state compatibility for driver signals before assigning refinement model to a circuit component
Significantly improve import of Circuits models from Verilog netlist
Enable selection of work file name for top module
Apply natural sort to imported Verilog modules
JavaScript interface to select save directory for instantiated Verilog modules via setImportContextDirectory(path)
that only spans for one import call
JavaScript interface to define the name of top module for import
Configurable pattern for work file names to save hierarchical Verilog modules ($.circuit.work
by default, where $
is replaced by module name)
Handle import of mutex with missing pins
Support bus connection syntax on Verilog import: explicitly enumerated nets of a bus .port({bus[2], bus[1], bus[0]})
, range of nets from a bus .port(bus[3:0])
, whole bus to a matching port .port(bus)
, mixture of net ranges and individual bits .port({bus[2:1], bus[0]})
Fixes and technical stuff
Update of the build system to Gradle v7.6, PMD v6.52, Apache Batik v1.16
New property type for color-coded legend
Support for printing Boolean expression in C style
Prevent clashing of flat names derived from Circuit hierarchical references
Simplify file writer operations without the use of dedicated exporter
Refactor
API for importer and exporter plugins
Speed up extraction of model type from work file
Clear JavaScript tab after script submission
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