Allow different file names for imported hierarchical and non-hierarchical Verilog modules
Invert sequential gates by swapping their set and reset functions
Add several predefined choice options for common cell libraries
Enable use of environment variables in cell library path
Set initial state to 1 for instantiated TIE1 cells
Add tooltips to instantiation panel showing cell area
Extend workcraft.lib with MAJ3/MAJI3, AOA212/AOAI212, OAO212/OAOI212 and add several positive gates (e.g. AO222 and OA222) for existing negative counterparts
New transformation command for auto-connecting hanging pins of circuit instances to ports with the same names
Move path-breaker and force-init tags to detached output inverter
Optimise scan and reset insertion with gate remapping
Update gate initial state on its inversion toggle
Move initial state and path-breaker tags of contracted gate to its driver
Skip buffering high fanout driven by a constant