31 July - 02 August 2018 at Dialog Semiconductor, Campbell, USA

At this course we will start from the theory and fundamental principles of asynchronous circuit design. Then we will proceed to the advanced techniques for technology mapping, and verification and synthesis of hierarchical designs. Practical session will teach the engineer how to use the Workcraft toolset to synthesise and verify asynchronous circuits, such as buck controller and VME bus controller.

• Lectures (3 hours)
  • Asynchronous design principles, models, techniques, and tools – slides (2 MiB)
  • Logic synthesis from STGs and implementation styles – slides (372 KiB)

• Practicals (3-4 hours)
  • Introduction to Workcraft – handouts (279 KiB)
  • Design of C-element
  • Design of basic buck controller

• Lectures (3 hours)
  • Modelling and decomposition techniques – slides (2 MiB)
    • Examples of modelling joint OR causality: or-joint-2bounded.stg.work (3 KiB), or-joint-1safe.stg.work (3 KiB)
  • Analog-to-asynchronous (A2A) interfaces – slides (497 KiB)
  • CSC conflict resolution – slides (522 KiB)

• Practicals (3-4 hours)
  • Hierarchical design of a realistic buck controller
  • Initialisation of speed-independent circuits
  • Resolution of encoding conflicts

• Lectures (2 hours)
  • Logic decomposition and technology mapping – slides (808 KiB)
  • N-way conformation – slides (61 KiB)

• Practicals (3 hours)
  • Logic decomposition and technology mapping
  • Verification and synthesis of hierarchical designs