Advanced Design of Asynchronous Circuits
11-12 July 2019 at Dialog Semiconductor, Germiring, Germany
This course covers a variety of advanced topics, including logic decomposition and technology mapping for complex STGs, and also initialisation and testing of speed-independent circuits.
Day 1: Initialisation, loop breaking, hierarchy
N-way conformation
Lecture and demo (30 min) –
slides (216 KiB)
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Day 2: Logic decomposition, technology mapping, timing conditions
Design of interrupt handler (30 min) –
slides (1 MiB)
Design with timing conditions (30 min) –
slides (795 KiB)
Demo of
Verimap for converting single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks (30 min)
Vision and discussion for functional verification using async-SVA (1 hour) –
slides ( B)