11-12 July 2019 at Dialog Semiconductor, Germiring, Germany

This course covers a variety of advanced topics, including logic decomposition and technology mapping for complex STGs, and also initialisation and testing of speed-independent circuits.

• Initialisation of speed-independent circuits
  • Lecture and demo (30 min) – slides (753 KiB), examples (41 KiB)
  • Practical (1 hour) – Initialisation of speed-independent circuits

• Loop breaking and testing
  • Lecture and demo (30 min) – slides (630 KiB), examples (27 KiB)
  • Practical (1 hour) – Loop breaking and offline testing

• N-way conformation
  • Lecture and demo (30 min) – slides (216 KiB)
  • Practical (1 hour) – Verification and synthesis of hierarchical designs

• Support for hierarchical design in Workcraft
  • Vision on automation and reuse (30 min) – slides (749 KiB)
  • Demo of progress so far (30 min)

• Logic decomposition and Technology mapping
  • Lecture (1 hour) – slides (681 KiB)
  • Surgery of interesting STGs (1 hour)
  • Practical (1 hours) – Logic decomposition and technology mapping

• Design of interrupt handler (30 min) – slides (1 MiB)

• Design with timing conditions (30 min) – slides (795 KiB)

• Demo of Verimap for converting single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks (30 min)

• Private demos and discussions (2 hours)