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Digital Circuit plugin

Familiarise yourself with Workcraft interface to learn its common features that are available for all plugins.

This plugin is intended for capturing, simulation and verification of asynchronous digital circuits. For simulation and verification the circuit is automatically translated into a Signal Transition Graph (STG) that allows re-using the features of the STG plugin.


In order to create a circuit model choose File→Create work… menu item and in the New work dialogue select Digital Circuit as the model type.

New work of Signal Transition Graph type

Functional components

The main building blocks of a digital circuit are functional components that can be created with the function generator [F] Function. Initially a generated component has only a single output pin (z0 by default). New pins can be added through the Add output or Add input items of the popup menu (accessible by right-clicking the component). The pin name and type can be changed in the property editor – see Name and I/O type properties respectively.

Generating a new component

Initially the output pin has neither set nor reset functions assigned. The set/reset functions can be specified by selecting the output pin and entering the corresponding Boolean expressions in the Set function and Reset function entries of the property editor. Note that if a component has a single output pin (which if is the majority of logic gates) then the set/reset functions can be also modified in the properties of the component.

Assigning set/reset functions

A component visualisation is defined by its Render type selected in the property editor, as follows:

  • Box – the component is visualises as a box with explicitly named pins and their set and reset functions rendered next to them. This render type is convenient when a component has more than one output or its set/reset functions are too complex.
  • Gate – the set and reset functions of a single component output are visualised using the traditional graphical mnemonics for Boolean operations. The obtained result is free of textual information (even the pins are not labelled) and therefore is usually easier to comprehend. Rendering a component as gate is convenient when it has a single output with relatively simple set/reset functions. This is the default rendering type with the following visualisation rules:
    • If both set and reset functions are specified then the component is rendered as a C-element.
    • If only the set function is specified, then the reset function is assumed to be complimentary and the component is rendered as a combinational gate (possibly with several layers of logic).
    • If the component cannot be rendered as a gate, e.g. because its set function is not empty or it has several output pins, then the Box visualisation is used.

Function rendered as a gate and as a box

Usually it is not necessary to explicitly create input pins. When a Set function or Reset function is entered for an output pin, the missing input pins are automatically created for all the literals in the Boolean expressions. Note that the input pins do not disappear if they become unneeded after modification of the set/reset functions. You may need to manually remove those pins by first selecting them and then pressing Delete button.

Input and output ports

Other building blocks of a digital circuit are its primary input and output ports. These are used to interact with the circuit environment. The ports are created with the port generator [P] Input/Output port – just activate this editor tool and click the editor panel in a position you want to place the port. By default an output port is created, however, if you hold Shift while clicking the editor panel then an input port is created. Note that you can change the of existing port I/O type in the property editor too.

Input and output ports


When the connection tool [C] Connect is active you can connect the pins of the circuit components and primary ports. The output pins and the input ports can be connected either to the input pins or to the output ports. Several connections may start at the same output pin or an input port, however, only a single connection can end up at an input pin or an output port. If an incorrect connection is attempted (e.g. a connection from an input pin to an output port or more than one connections to an input pin) then a warning message will be issued.

Invalid connection

In order to reduce the number of arcs going from the same output pin (or an input port) and simplify the layout of the connection arc, one can “fork” the wires – just start a connection from an existing wire and a joint point will be automatically created. New connections can be also started from the existing joint points.

Connections with forks


For editing the model activate the selection tool [S] Select. All the standard editing features (select, drag-and-drop, delete, copy, undo, group, etc.) work the same – see generic help on Selection controls and Property editor for details.

Similar to all the other models, textual comments can be created by activating the [N] Text Note tool and clicking the editor panel in the position you want to put the text. Double-click on the note box to edit its text label in-place or do it through the property editor panel when the note is selected.


For simulation of a Digital Circuit model activate the simulation tool [M] Simulate. The enabled pins and ports are highlighted and can be activated by clicking them. The simulation tool controls provide the means for analysis and navigation through the simulation trace, see generic help on Simulation controls for details. The circuit simulation is just an abstraction over the simulation of an automatically generated STG representation of the circuit components. Therefore all the specifics of STG simulation also apply to the Digital Circuit plugin.

The state of circuit's signals is visualised by colouring the corresponding pins and wires either blue (for logical 0) or red (logical 1). Circuit pins associated with excited signals are highlighted and can be clicked to progress to the next state.

By default the circuit driver pins (input ports and the gate output contacts) are initialised to logical 0. This may lead to some of the circuit internal signals being excited when the simulation begins, e.g. the output out0 is 0, but evaluates to 1 (first transition in the simulation trace). There are two ways to change the initial values to the circuit signals:

  • A driver pin can be set to logical 1 by ticking the Init to one property of the pin.
  • Alternatively, in simulation mode, when a desired association of signal values is reached, this state can be saved as the initial state of the circuit by pressing this button – Save current state as initial.

Circuit simulation

A circuit simulation trace can be converted to a Digital Timing Diagram by the generator of trace diagram Generate trace diagram. The order, visibility, and color of signal waveforms are specified in the signal state table – see STG simulation help for details.

Timing diagram for circuit simulation trace


Verification of a digital circuit is usually made in the context of its environment. The environment can be described as an STG and attached to the circuit model using the property editor when no nodes are selected.

When a verification task is issued via the Verification menu, the circuit is first translated into an STG that is subsequently composed with the STG of the environment. The resultant STG is used for verification of the desired properties:

  • Conformation [MPSat] – verify if the circuit conforms to the environment specification.
  • Deadlock freeness [MPSat] – verify if the circuit is deadlock-free.
  • Output persistency [MPSat] – verify if the circuit is output-persistent.
  • Conformation, deadlock freeness, output persistency (reuse unfolding) [MPSat] – verify if the circuit conforms to the environment specification, is deadlock-free and output-persistent under the given environment.

Initialisation analyser

Initialisation (or reset) of a speed-independent circuit is an important part of the design process because a circuit can malfunction if its initial state is incorrect. Note that the initialisation phase of a speed-independent circuit does not have to be speed-independent: It is assumed that there is a special reset signal that is generated externally and behaves as follows:

  • When the power is connected, reset is low.
  • It stays low for sufficiently long time to complete the initialisation of all gates.
  • Eventually reset goes high, at which point the circuit is already correctly initialised and the normal speed-independent operation begins.
  • reset stays high for the whole time of circuit normal operation.

There are several ways of circuit initialisation that can be used in combination:

  • Rely on the initial state of some of the inputs (which are guaranteed to be correctly initialised by the environment). They propagate through some of the logic gates to initialise some of the internal and output signals.
  • Substitute some of the gates with ones containing an extra input that can act as a set or reset pin.
  • Insert additional gates to explicitly initialise the internal and output signals. Such gates will act as buffers during the normal operation, so one has to be careful not to break any isochronic forks.

Initialisation analyser [I] Initialisation analyser tool is designed to aid the decision of how to reset these modules. The tool uses Init to one and Forced init properties of circuit signals (i.e. primary input ports and output pins of circuit components):

  • Init to one property defines the initial state of the signal. If a circuit is synthesised by one of the backend tools, then the initial state of all its signals is set automatically. However, if the circuit is manually altered, then the designer is responsible for specifying the initial states of the signals.
  • Forced init property defines if the signal is known to be in a correct initial state. For a primary input it means the environment takes care of initialising the signal to its expected state. For a component output pin it means that the necessary circuitry will be added to properly initialise that pin.

These properties can be viewed and modified in the Property editor when an input port or an output pin is selected. Note that selecting a single-output component (i.e. a gate) also reveals these properties of its only output pin.

Initialisation analyser uses these properties as follows. It considers the signals whose Forced init property is set as initialised, while the remaining signals are assumed as uninitialised. The tool tries to evaluate each uninitialised signal on the Init to one property of initialised signals. If the Boolean value of a signal can be derived, then it is said to have propagated initial state and the signal is also considered initialised. The tool repeats evaluation of uninitialised signals until no further progress can be made, i.e. no new initialised signals can be obtained. At this stage, if some signals are still uninitialised it means Forced init property of the circuit signals needs to be adjusted, until all the signals are successfully initialised.

If the propagated initial state of a signal does not match its Init to one property, then the signal is said to have initialisation conflict – this often indicates a mistake, e.g. incorrect initial value of the signal. However, there are legitimate situations where such conflicts can occur – most likely such a signal needs to be explicitly initialised by setting its Forced init property.

Initialisation analyser visualises the initialisation state using the Gate highlight legend shown in the Tool controls:

By default the highlighting scheme is as follows (the colours can be adjusted in the preferences of digital circuit model – see Edit→Preferences…→Models→Digital Circuit):

  • The wires and pins of initialised signals are coloured red (if Init to one property is set) or blue (if Init to one is not set). Wires and pins of uninitialised signals are coloured black.
  • Components whose initial state cannot be determined via propagation of forced signals are not highlighted (i.e. remain white).
  • In case of initialisation conflicts, the problematic gates are highlighted magenta.
  • Output pins whose Forced init property is set are visualised by diamond shape and their components are highlighted orange.
  • Correctly initialised components are highlighted green.

Force init pins table enumerates the pins whose Forced init property is set. Note that Forced init property of a signal can be toggled while in Initialisation analyser tool by clicking the corresponding input port, output pin, or a gate. This enables convenient exploration of possible reset strategies. The tool also provides several ways of changing Force init property for a group of contacts:

  • Clear force init from all input ports and component outputs - Unset Forced init property for all input ports and component outputs.
  • Toggle force init for all input ports (environment responsibility) - Toggle Forced init property for all input ports. Note that it is the environment responsibility to guarantee the correct initialisation of primary inputs whose Forced init property is set.
  • Toggle force init for all self-loops - Toggle Forced init property for all component outputs with self-loops.
  • Toggle force init for all sequential gates - Toggle Forced init property for outputs of all sequential gates.
  • Remove force init from pins if redundant for initialisation - Unset Forced init property of the component outputs if they are redundant for the circuit initialisation.
  • Add force init to pins if necessary to complete initialisation - Set Forced init property of component outputs as necessary to complete initialisation of the circuit.

Circuit initialisation comprises three steps:

  1. Reset exploration – Decide which signals should be forced to the initial state, so that the correct initial values propagate to the remaining circuit components. Selecting a good set of forced signals is a creative process with multiple optimisation targets (avoiding critical paths, circuit size, gate complexity, etc.) and relies on designer experience.
  2. Reset insertion – Insert the reset port reset, set its Init to one property according to the reset active state (false for active low, true for active high), and use it to initialise all the signals that have Force init property set.
  3. Reset validation – Clear Force init property of all component pins and input ports, set Force init property for the reset port, and check that all the circuit components are correctly initialised.

Consider our circuit example whose all signals are initially expected (but not guaranteed!) to be 0, i.e. none of the driver pins have their Init to one property set. Let us explore initialisation strategies by activating Initialisation analyser [I] Initialisation analyser. As no Forced init property is set the initial state of all the circuit signals is undefined:

Undefined initialisation state

Let us assume that circuit's environment forces all the input ports to be in the expected state and indicate this by setting their Forced init property. This can be achieved by either clicking each input port, or by pressing Toggle force init for all input ports (environment responsibility) button. The result is as follows:

Initialisation conflict

One can see that the C-element g1 has been properly initialised via its inputs – it is highlighted in green. However, the initial state of gate g0 contradicts the propagated value from the input ports – it is highlighted in magenta. The conflict on g0 output is visualised as follows: the contact is blue (represents the expected value 0), while its outline is red (representing the propagated value 1).

Address this issue by forcing g0 to the expected initial state. For this click the gate – its highlighting color should change to orange indicating that it is the designers responsibility to force this gate to the expected state:

Forced initial state

Now the circuit does not have any initialisation conflicts, however, its gate g0 needs to be explicitly reset. This can be done automatically by pressing Insert reset logic button. The following dialog request the name of reset port and its active state (active-low or active-high):

Reset properties

Here is a result of inserting active-high reset (g0 function is modified to be resetable to 0, an input port reset is added and connected to the new pin of g0):

Insertion of reset logic

Now the circuit is correctly initialised via its primary inputs – all the gates are highlighted in green to indicate this. Note that the newly inserted reset port is constrained by its set and reset functions, therefore the circuit can be verified against the original environment STG without reset signal.