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Design Automation for AMS Circuits with Asynchronous Control

11 December 2016 at ICECS-2016, Monte Carlo, Monaco

AMS engineers are increasingly involved in designing AMS electronics with a significant portion of digital elements in them. Examples include programmable and pipelined ADCs, complex power management circuits such as multi-phase buck converters, switched-capacitor circuits, etc. Specific reasons for having more digital components are the increasing complexity and functionality of AMS, as well as the migration of mixed signal towards ultra-deep sub-micron technologies. According to Andrew Talbot from Intel, recently speaking at the AMS workshop at RAL, “transistors are very fast switches, netlists are huge, parasitics are phenomenally difficult to estimate, passives don’t follow Moore’s law, reliability is a brand new landscape.”. Digital parts in them often perform functions such as calibration control, parameter configuration, switching control, “monitoring and knobbing”, etc. We call such digital (on-top or within analogue) electronics “little digital” as opposed to “big digital” (i.e. traditional computational) electronics. Designing “little digital” is hard because it should seamlessly integrate with the analogue parts, which are dynamic and notoriously hard to automate. Using standard design flows such as RTL, which is driven by a clock, is not a good option for “little digital” because analogue circuits have their own notion of timing and events. The clocked operation mode, natural for the data processing (in “big digital”), might lead to either low responsiveness or power consumption overheads in control modules of mixed-signal systems. On the one hand, the operating frequency must be sufficiently high to promptly react to changes in analogue sensor readings. On the other hand, high clocking frequency can potentially result in wasted clock cycles if the sensors’ readings change slowly. Asynchronous circuits can provide greater robustness, reactivity, and power efficiency. However, due to the lack of knowledge of the methods and awareness and trust in the available (mostly academic) CAD tools for asynchronous design, the majority of AMS engineers have to rely on ad hoc development approaches and use extensive simulation to prove correctness of their designs.

We will introduce a new and steadily evolving design flow for AMS systems with asynchronous control, developed at Newcastle University in collaboration with the University of Utah. The flow is based on the use of event-based models such as Petri nets and Signal Transition Graphs (STGs), and implemented in a tool-suite called Workcraft. Workcraft is publicly available from and has an increasing number of users, both academic and industrial. This flow has already been used at Dialog Semiconductor with success. The tutorial will consist of two parts. In the first part we will concentrate on the use of existing Workcraft tools for designing asynchronous controllers – we will show how the new design flow can be applied to designing asynchronous control for multi-phase buck converters, ADCs, interfaces, SRAM controllers, etc. In the second part of the tutorial, we will present the most recent theoretical and algorithmic developments targeted at the design optimization of the holistic AMS systems involving formal verification of their analogue parts. The method involves co-simulation of analogue and digital parts, extraction of traces and construction of Petri net models from simulation traces; these models are then used for AMS verification and optimization of the digital asynchronous parts.


  • Introduction and motivation (15 mins)
  • Asynchronous design for Analogue electronics (60 mins)
    • Basics of asynchronous design
    • Formal specification
    • Circuit synthesis
    • Verification
  • Design examples (45 mins)
    • SRAM controller
    • Multiphase buck converter
    • Asynchronous ADC
    • Workcraft tool demo
  • AMS design with asynchronous control (60 min)
    • Co-design flow: Workcraft and LEMA
    • Simulation-driven analogue model generation
    • Control optimization and analogue verification


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