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help:scripting

Scripting interface

Workcraft supports scripting using JavaScript language.

The JavaScript can be passed as script.js file:

./workcraft -nogui -exec:script.js

For a short JavaScript snippet it may be more convenient to pass it directly in the command line:

./workcraft -nogui -exec:<(echo 'JAVASCRIPT CODE')

Here is several examples of JavaScript code:

// Mirror signals and untoggle transitions of STG model
inStg = load("in.stg.work");
tmpStg = executeCommand(inStg, "MirrorSignalTransformationCommand");
outStg = executeCommand(tmpStg, "PetrifyUntoggleConversionCommand");
save(outStg, "out.stg.work");
exit();
// Complex gate implementation for basic buck controller
stg = load("buck.stg.work");
circuit = executeCommand(stg, "PetrifyComplexGateSynthesisCommand");
save(circuit, "buck.circuit.work");
export(circuit, "buck.v", "VERILOG");
exit();
// Technology mapping of VME bus controller into Faraday library
// (CSC conflict resolution with Petrify, synthesis with MPSat)
stg = import("vme.g");
cscStg = executeCommand(stg, "PetrifyCscConflictResolutionCommand");
setConfigVar("CircuitSettings.gateLibrary", "path-to-genlib-faraday.lib");
circuit = executeCommand(cscStg, "MpsatTechnologyMappingSynthesisCommand");
export(circuit, "vme.v", "VERILOG");
exit();

These examples use the following function shortcuts defined in functions.js resource file that is automatically read on Workcraft startup.

File operations

  • load(path) – load the work file path and return its WorkspaceEntry
  • import(path) – import model from the file path and return its WorkspaceEntry; the model type is detected by the file extension
    • .gASTG file for a STG model
    • .sgASTG file for a FST model
    • .vVerilog netlist file for a circuit model
  • save(work, path) – save the WorkspaceEntry work into a file path
  • export(work, path, format) – export the WorkspaceEntry work into a file path with the supported format:
    • “SVG” – export any visual model as a Scalable Vector Graphics .svg file
    • “PNG” – export any visual model as a Portable Network Graphics .png file
    • “PDF” – export any visual model as a Portable Document Format .pdf file
    • “PS” – export any visual model as a PostScript .ps file
    • “EPS” – export any visual model as an Encapsulated PostScript .eps file
    • “DOT” – export any visual model as a GraphViz .dot file
    • STG – export STG or Petri net model as an ASTG .g file
    • “SG” – export FSM or FST as an ASTG .sg file
    • “VERILOG” – export circuit model as a Verilog netlist .v file
    • “SDC” – export circuit model as a Synopsys Design Constraints .sdc file (work in progress)

Configuration

  • setConfigVar(key, val) – set the config variable key to value val
  • getConfigVar(key) – return the value of config variable key
  • saveConfig() – save settings into the default config file
  • loadConfig() – load settings from the default config file

Command execution

  • execFile(path) – execute JavaScript file path
  • execResource(name) – execute JavaScript resource name
  • runCommand(work, className) – apply command className to WorkspaceEntry work, possibly as a background task
  • executeCommand(work, className) – return a WorkspaceEntry which is the result of command className applied to WorkspaceEntry work; the following types of commands can be executed:
    • Transformation – commands inherited from AbstractTransformationCommand, e.g.:
      • “ExplicitPlaceTransformationCommand” – make places of the STG model explicit
      • “MirrorSignalTransformationCommand” – mirror signals of the STG model
      • “ReadArcToDualArcTransformationCommand” – convert read-arcs of the STG or PN model to dual producing/consuming arcs
    • Layout – commands inherited from AbstractLayoutCommand, e.g.:
      • “DotLayoutCommand” – node positioning and connection shape calculated by Graphviz backend.
      • “CircuitLayoutCommand” – position circuit components according to their ranking in the netlist connectivity graph
    • Conversion – commands inherited from AbstractConversionCommand, e.g.:
      • “CircuitToStgConversionCommand” – generate STG (circuit Petri net) for the circuit model
      • “StgToBinaryFstConversionCommand” – build a binary-encoded FST model (state graph) for the STG model using Petrify backend
      • “PetrifyHideDummyConversionCommand” – hide dummies in the STG model using Petrify backend
    • Synthesis – commands inherited from AbstractSynthesisCommand, e.g.:
      • “PetrifyComplexGateSynthesisCommand” – logic synthesis of the STG into a complex gate circuit using Petrify backend
      • “MpsatStandardCelementSynthesisCommand” – logic synthesis of the STG into a standard C-element circuit implementation using MPSat backend
      • “MpsatTechnologyMappingSynthesisCommand” – technology mapping of the STG into a circuit using MPSat backend

Miscileneous

  • print(msg) – output the message msg to stdout
  • println(msg) – output the message msg to stdout and add a new line
  • printErr(msg) – output the message msg to stderr
  • printlnErr(msg) – output the message msg to stderr and add a new line
  • startGUI() – start GUI
  • stopGUI() or shutdownGUI() – stop GUI
  • quit() or exit() or shutdown() – exit Workcraft