// Technology mapping of the specified .g files whose names are passed // without extension, as follows: // workcraft -dir:WORKING_DIRECTORY_PATH -exec:synth.js TEST1 TEST2 setConfigVar("CircuitSettings.gateLibrary", "path-to-genlib-file"); for each (name in args) { stgWork = import(name + ".g"); if (stgWork == null) { eprint("STG work loading failed!"); exit(); } if (checkStgCsc(stgWork) == true) { cscStgWork = stgWork; } else { cscStgWork = resolveCscConflictPetrify(stgWork); if (cscStgWork == null) { eprint("CSC conflict resolution failed!"); exit(); } save(cscStgWork, "vme-csc.stg.work"); } tmCircuitWork = synthTechnologyMappingMpsat(cscStgWork); if (tmCircuitWork == null) { eprint("Circuit synthesis failed!"); exit(); } if (checkCircuitCombined(tmCircuitWork) == true) { exportVerilog(tmCircuitWork, name + ".v"); } else { eprint("Circuit verification failed!"); } } exit();