// Define circuit initialisation scheme and insert active-low reset
// (requires Workcraft v3.2.3 or newer)
work = load("test-tm.circuit.work");
if (checkCircuitCombined(work) != true) {
    eprint("Circuit verification failed");
    exit();
}
tagCircuitForcedInitClearAll(work);
tagCircuitForcedInitInputPorts(work);
tagCircuitForcedInitAutoAppend(work);
insertCircuitResetActiveLow(work);
if (checkCircuitReset(work) != true) {
    eprint("Circuit cannot be reset to the required initial state");
    exit();
}
if (checkCircuitCombined(work) != true) {
    eprint("Circuit verification failed after reset insertion");
    exit();
}
exportVerilog(work, "test-tm-reset.v");
exit();