Overview

A large number of models that are employed in the field of concurrent systems design, such as Petri nets, gate-level circuits, dataflow structures, etc. - all have an underlying static graph structure. Their semantics, however, is defined using additional entities, e.g. tokens or node/arc states, which in turn form the overall state of the system. We jointly refer to such formalisms as interpreted graph models. The similarities between the interpreted graph models allow for links between different formalisms to be created, either by means of adapter interfaces or by conversion from one model type into another. This greatly extends the range of applicable modelling and analysis techniques.

Workcraft is designed to provide a flexible common framework for development of interpreted graph models, including visual editing, (co)simulation and analysis. The latter can be carried out either directly or by mapping a model into a behaviourally equivalent model of a different type (usually a Petri net). Hence the user can design a system using the most appropriate formalism (or even different formalisms for the subsystems), while still utilising the power of Petri net analysis techniques. Below is a summary of the currently supported interpreted graph models that are implemented as as plug-ins for Workcraft framework.

Model	Supported features
Model	Editing	Simulation	Verification	Synthesis
abstract behaviour
Directed Graph [1]	Yes	Yes	Yes	n/a
Finite State Machine [2]	Yes	Yes	Yes	Yes¹⁾
Petri Net [3]	Yes	Yes	Yes	Yes²⁾
Policy Net [4]	Yes	Yes	Yes	Yes³⁾
signal semantics
Digital Timing Diagram [5]	Yes	No	No	n/a
Waveform Transition Graph [6]	Yes	Yes	Some	Yes⁴⁾
Finite State Transducer [7]	Yes	Yes	Yes	Yes⁵⁾
Signal Transition Graph [8]	Yes	Yes	Yes	Yes⁶⁾
Conditional Partial Order Graph [9]	Yes	Some	No	Yes⁷⁾
structural information
Structured Occurrence Net [10]	Yes	Yes	Yes	n/a
Dataflow Structure [11]	Yes	Yes	Yes	No
Digital Circuit [12]	Yes	Yes	Yes	n/a
xMAS Circuit [13]	Yes	Yes	Some	No

overview:model_relationship.svg

[1] Directed Graph.

[2] Finite State Machine.

[3] Petri net.

[4] J. Fernandes, M. Koutny, M. Pietkiewicz-Koutny, D. Sokolov, A. Yakovlev: “Step persistence in the design of GALS systems”, Proc. International Conference on Application and Theory of Petri Nets (ATPN), pp. 190–209, 2013.

[5] Digital Timing Diagram.

[6] J. Cortadella, A. Moreno, D. Sokolov, A. Yakovlev, D. Lloyd: “Waveform transition graphs: A designer-friendly formalism for asynchronous behaviours”, Proc. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2017.

[7] Finite State Transducer.

[8] A. Yakovlev, L. Lavagno, A. Sangiovanni-Vincentelli: “A unified signal transition graph model for asynchronous control circuit synthesis”, Formal Methods in System Design, vol. 9(3), pp. 139–188, 1996.

[9] A. Mokhov, A. Yakovlev: “Conditional partial order graphs: model, synthesis and application”, IEEE Transactions on Computers, vol. 59(11), pp. 1480–1493, 2010.

[10] M. Koutny, B. Randell: “Structured occurrence nets: a formalism for aiding system failure prevention and analysis techniques”, Fundamenta Informaticae, vol. 97(1–2), pp. 41–91, 2009.

[11] D. Sokolov, I. Poliakov, A. Yakovlev: “Analysis of static data flow structures”, Fundamenta Informaticae, vol. 88(4), pp. 581–610, 2008.

[12] I. Poliakov, A. Mokhov, A. Rafiev, D. Sokolov, A. Yakovlev: “Automated verification of asynchronous circuits using circuit Petri nets”, Proc. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 161–170, 2008.

[13] S. Chatterjee, M. Kishinevsky, U. Ogras: “Quick formal modeling of communication fabrics to enable veriﬁcation”, Proc. IEEE International Workshop on High Level Design Validation and Test (HLDVT), pp. 42–49, 2010.

¹⁾ , ³⁾

synthesis into Petri Net

²⁾

re-synthesis into simpler Petri Net

⁴⁾

via translation to synthesisable Signal Transition Graph

⁵⁾

into Signal Transition Graph

⁶⁾

synthesis into Digital Circuit and re-synthesis into simpler Petri Net

⁷⁾

synthesis into Digital Circuit