On circuit wire routing align first/last control points to adjacent pins.
Recognise MUTEX elements on Verilog import.
Convert trivial assign statements in Petrify output for technology mapping into BUF instances.
Compatibility checks for circuit and its environment before proceeding with verification.
Improve deadlock verification for circuits, taking into account that it cannot be reliably checked in case of conformation violation.
Signal Transition Graph plugin
Verification of STG for output determinacy, i.e. that the STG is not self-contradictory.
Verification of N-way conformation for STGs with dummies (previously dummies were forbidden for technical reasons).
Corrections for visualisation and .g export of the promised place capacity.
In STG simulation highlight arcs with implicit marked place.
Fixes and technical stuff
Updated UnfoldingTools backend to support -Fe mode of MPsat – work out the complete trace (including the trailing dummies) to the violation.
Command line option to start Workcraft without loading/overwriting user config – this useful for scripting.
Global setting Use short header in exported files that allows skipping Workcraft version in the file header (useful for scripting and regression testing).
Use external JavaBeans Activation Framework (JAF) for compatibility with the newer versions of JVM (JAF was deprecated in Java 9).
Prevent inconsistent state of Property editor.
Simplified API for Mathematical and Visual models.