User Tools

Site Tools


help:assertion

Assertion language

Assertions can be specified similar to System Verilog syntax, e.g. !(req1 && ack2) – declare that req1 and ack2 signals are never high at the same time.

The following logical operators are currently supported, in the order of increasing precedence:

  • ?: – conditional expression;
  • -> – implication;
  • || – disjunction;
  • && – conjunction;
  • ==, != – equivalence and inequality;
  • ! – negation.