<?xml version="1.0" encoding="UTF-8"?>
<!-- generator="FeedCreator 1.8" -->
<?xml-stylesheet href="http://workcraft.org/lib/exe/css.php?s=feed" type="text/css"?>
<rdf:RDF
    xmlns="http://purl.org/rss/1.0/"
    xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
    xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
    xmlns:dc="http://purl.org/dc/elements/1.1/">
    <channel rdf:about="http://workcraft.org/feed.php">
        <title>Workcraft - help:circuit</title>
        <description></description>
        <link>http://workcraft.org/</link>
        <image rdf:resource="http://workcraft.org/_media/logo.svg" />
       <dc:date>2026-05-07T12:35:05+00:00</dc:date>
        <items>
            <rdf:Seq>
                <rdf:li rdf:resource="http://workcraft.org/help/circuit/initialisation?rev=1559316701&amp;do=diff"/>
                <rdf:li rdf:resource="http://workcraft.org/help/circuit/loop_breaking?rev=1643646265&amp;do=diff"/>
                <rdf:li rdf:resource="http://workcraft.org/help/circuit/start?rev=1591732391&amp;do=diff"/>
            </rdf:Seq>
        </items>
    </channel>
    <image rdf:about="http://workcraft.org/_media/logo.svg">
        <title>Workcraft</title>
        <link>http://workcraft.org/</link>
        <url>http://workcraft.org/_media/logo.svg</url>
    </image>
    <item rdf:about="http://workcraft.org/help/circuit/initialisation?rev=1559316701&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2019-05-31T15:31:41+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>initialisation</title>
        <link>http://workcraft.org/help/circuit/initialisation?rev=1559316701&amp;do=diff</link>
        <description>Initialisation analyser

Initialisation (or reset) of a speed-independent circuit is an important part of the design process because a circuit can malfunction if its initial state is incorrect. Note that the initialisation phase of a speed-independent circuit does not have to be speed-independent: It is assumed that there is a special</description>
    </item>
    <item rdf:about="http://workcraft.org/help/circuit/loop_breaking?rev=1643646265&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2022-01-31T16:24:25+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>loop_breaking</title>
        <link>http://workcraft.org/help/circuit/loop_breaking?rev=1643646265&amp;do=diff</link>
        <description>Cycle analyser

Combinational cycles are common in asynchronous circuits -- they (along with latches) usually implement “memory” of the circuit. Verilog netlist for such cyclic circuits, however, may upset conventional EDA tools for timing analysis (e.g. Synopsys PrimeTime) and offline testing (e.g. Synopsys TetraMAX):   </description>
    </item>
    <item rdf:about="http://workcraft.org/help/circuit/start?rev=1591732391&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2020-06-09T19:53:11+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>start</title>
        <link>http://workcraft.org/help/circuit/start?rev=1591732391&amp;do=diff</link>
        <description>Digital Circuit plugin

Familiarise yourself with Workcraft interface to learn its common features that are available for all plugins.

This plugin is intended for capturing, simulation and verification of asynchronous digital circuits. For simulation and verification the circuit is automatically translated into a Signal Transition Graph (   </description>
    </item>
</rdf:RDF>
