Notes on Digital Circuit model

Circuit structural restrictions

Input port cannot be directly connected to output port.
Zero delay component cannot be connected to output port.
Zero delay components cannot be connected to each other.
Environment component cannot be connected to output port.
Can environment components be connected to each other (directly or via zero delay component?

Copy the hierarchy structure from the circuit to the STG.
Associate each circuit input/output port p with an STG input/output signal p at the same level of hierarchy.
Option 1: Pages for all components
- For each circuit component c create an STG page c at the same level of hierarchy. Associate each driver pin d of the circuit component c with an STG internal signal d inside the page c.
- For every signal x create a pair of places x_LOW and x_HIGH representing low and high levels respectively and insert the necessary number of transitions x+ and x- between these places.
- After conversion remove empty pages, e.g. those from circuit components who do not have driver pins.
Option 2 Pages for multi-output components only
- Associate each single-output non-environment circuit component g with an STG signal g at the same level of hierarchy.
  What to do with the “hanging” input pins of such components?
- For each circuit component c with more than one output create an STG page c at the same level of hierarchy. Associate each output o of the circuit component c with an STG signal o placed inside the newly created page c.
  What to do with pins directly connected to output ports?