changelog:v3.5.5
Workcraft v3.5.5 (2026-06-26)
Usability improvements
- Check validity of user defined exceptions
- Add tool name to the title of Tool controls
- Enable box selection of children nodes such as control points of connection and pins of circuit component
- Ability to apply saving decision to all modified works
- Ask for saving untitled works on shutdown
- Improve performance of Output panel log
- Indicate change of Output, Problems and Tasks tabs
Model and tool plugins
- Digital Circuit plugin
- Allow different file names for imported hier and non-hier Verilog modules
- Invert sequential gate by swapping set/reset functions
- Add predefined choice options for cell libraries
- Enable use of environment variables in Circuit cell library path
- Set initial state to 1 for instantiated TIE1 cells
- Add tooltips to gate instance panel
- Add MAJ3/MAJI3, AO222 and OA222 cells to workcraft.lib
- Auto-connect hanging pins of circuit instances to ports with the same name
- Move path-breaker and force-init tags to detached output inverter
- Optimise scan and reset insertion with gate remapping
- Enable gate remapping with extra input pin
- Update gate InitToOne on its inversion toggle
- Move contracted gate InitToOne and PathBreaker to preceeding gate
- Skip buffering high fanout driven by const
- Signal Transition Graph plugin
- Transformation command to increment last numeral in selected STG transitions
- Save the initial state of signals in circuit-STG on export in .g and .sg files
- Silently ignore .mode and .initial state on .g import
- CFLT plugin
- Code refactoring
- Parser update
- Add unit tests
Technical stuff
- Update build system to Gradle v9.6.0, CheckStyle v13.6.0, PMD v7.25.0, CPD v4.0.20, JaCoCo v0.8.15
- Initialise plugins in predictable order
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