Improve Mutex and Wait assign statement models on Verilog export
Clear arbitration primitive attribute from Mutex and Wait on modification
Provide diagnostics if Mutex or Wait definition is missing
Enable configurable buffering of scanout with either buffer or inverter
Enumerate input and output ports in model-level Property editor
On Verilog import assign initial state of TIE cells even without initialisation pragmas
Fix lost connections after contraction circuit component whose output has proxies