Support for proxy contacts
Show the number of driven contacts next to the driver contact
Revise handling of mutex early/late protocols
Preserve zero-delay attribute on inversion toggling
Update pin range filter on gate library reload
Convert exporter of mapped circuit as Verilog assign statements into System Verilog
Improve Verilog import with split declaration of ports
Add initial support for pre-designed components
Support stdC synthesis with input inverters
Fix parsing of reset sub-function for gC assign statement