Distinguish arbitration primitives with metastability filter by drawing shield symbol (denotes protection from glitches)
Prevent reducing component size on pin insertion
Recalculate Set/Reset functions of a pin/port on removal of related pins/ports
Improve rendering of sequential gates as asymmetric C-elements
Support rendering of gates whose Boolean function uses the same literal multiple times
Inherit initial state of the component ports on its replacement by implementation circuit
Use the file path as a base directory for importing Verilog hierarchy
Use relative path and do not follow symbolic links for environment file
Warn on suspicious initial state at Verilog import
Add details about the module name into the messages about importing Verilog hierarchy
Append reset pin name to sequential gate label on reset insertion
Improve reset insertion into a circuit with LOGIC1/LOGIC0 components
Enable user-defined string as delay value for Verilog assign statements
Preserve output pins on change of other pins set/reset functions
Factor set function of MUTEX component with early protocol