Separate setting Open synthesis results as Digital Circuit for Petrify and MPSat backends.

Check for circuit integrity before component contraction.

New verification property Delay insensitive interface (without dummies) [MPSat].

Tool for mirroring polarity of STG signal transitions.

Forbid several connections between STG transitions (this leads to implicit places with ambiguous names and contradicts definition of STGs).

Non-ASCII characters are forbidden in Reach expression editor of custom verification properties.

Improvements for MPSat custom verification dialog.

Remove isolated marked places before calling Petrify, as such places are redundant but upset Petrify .g parser.

Warning on increase of place capacity during simulation.

Simulation tool is moved from Petri nets and STG plugins into Workcraft core.

Extended by vertex labelling function to serve as a basis for timing diagrams model.

Converter from Graph to Petri net.

Reuse of Petri net simulation engine for Graphs.

A tool for identifying unreachable vertices.

A new plugin to support visualisation and editing of timing diagrams.

Using connection tool to order signal events.

Movement of signal waveforms and signal edges is restricted by causality arcs.

Generating Edge and Pulse patterns of timing diagrams by clicking on the signal name and signal level respectively.

Converter from STG and Circuit simulation traces into timing diagram. It is activated by pressing the Generate trace diagram button in the simulation tool.

The order of signals in the timing diagram can be rearranged by drag-and-drop of the Signal state table rows in the simulation tool.

Configurable visibility and color of signals waveforms in the Signal state table.

CPOG algebra tools are moved to a dedicated Algebra menu.

Code for evaluation, rendering and minimisation of Boolean formulas is moved from CPOG plugin into Workcraft core.

Optimisation to enable rendering vertices as labels even in larger CPOG models.