Conversion of the simulation trace from the composed
STG (circuit
STG + environment
STG) into the circuit
STG. The trace is projected on the set of circuit signals (environment signals are skipped) and transition instances are adjusted.
Better support for hierarchical circuits (pre-processing of hierarchical traces, output ports and their drivers in different pages).
Circuit
STG is simplified by removing dead transitions and duplicate transitions (this can be switched off in global settings under
Digital Circuit→Simplify generated circuit STG).
A button to remove circuit environment is added to the
Environment URI property.
Improved validation of connections (forbid direct connection from input port to output port, forbid forks on several output ports).
The initial state of circuit signals for simulation is properly calculated.
Possibility to centre the pivot point of circuit components via popup menu.
CSC and USC checks report pairs of traces leading to the same state code. These traces can be played as Trace and Branch in simulation mode.
Flip and rotate operations for circuit components, ports and contacts.
Bounding box for circuit connections takes their names and set/reset functions into account.
Caching contact label glyphs to speed up circuit redraw.
Improvement to calculation of the circuit component size and pin location when rendered as a Box.