====== Loop breaking and offline testing ======

In this tutorial we will use VME bus controller circuit <wrap download>{{vme-tm.circuit.work}}</wrap> and its STG specification <wrap download>{{vme.stg.work}}</wrap> developed in the tutorial  [[tutorial:design:vme_bus:start|Design of VME bus controller]] -- download these files into your working directory.

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===== Analysis of combinational cycles =====

Open VME bus controller circuit and activate //Cycle analyser// {{help:circuit:editor_tools-cycle_analysis.png?nolink|[Y] Cycle analyser}} tool. Most of the gates are highlighted <color magenta>magenta</color> indicating that they belong to some combinational cycles:

{{ vme-tm-cycle_analysis.circuit.png?nolink |Cycle analysis of VME bus controller}}

If we would pass this circuit to a static timing analysis tool, it would likely disable the timing arc in gate ''OUT_BUBBLE15'' to eliminate all the cycles. While this is may look like an optimal solution, unfortunately it also removes many important timing paths, e.g. one would not be able to measure the critical delays from ''<color red>dsr</color>'' and from ''<color red>dsw</color>'' to ''<color blue>lds</color>''. Therefore, other methods of dealing with combinational cycles are required.

===== Disabling timing arcs =====

As a first exercise, experiment with tagging input pins in VME bus controller as path breakers, trying to eliminate all the combinational cycles. At the same time make sure to preserve all interesting and important timing paths.

For example, if we assume that feedback loops are always short and do not require timing analysis, then the self-loop input pin of gate ''U17'' is an obvious candidate for breaking a cycle. The input of ''U16'' that is driven by a zero delay inverter is another candidate for path breaking as it is not on a critical path. (Alternatively the timing arc in the preceding zero delay inverter can be disabled.) Click both these input pins to set their //Path breaker// property. The result should look as follows:

{{ vme-tm-break_timing_arcs-selfloops.circuit.png?nolink |Breaking self-loop timing arcs in VME circuit}}

It may be tempting to tag the remaining pin on the cycle in gate ''U16'' as a path breaker, and this indeed would eliminate all the cycles. However, this would also break an important path from ''<color blue>d</color>'' to ''<color blue>lds</color>'' while, according to the specification of VME bus controller, ''<color blue>d</color>'' is a trigger of ''<color blue>lds</color>'' (see  the causality arc ''<color blue>d+</color>-><color blue>lds+</color>'' in the STG below):

{{ vme.stg.svg?35%,nolink |}}

Instead, consider input pins in gates ''U1'' and  ''U5'' that are on a cycle. These are driven by context signals as all the triggers of  output ''<color blue>d</color>'' are primary inputs of the circuit. Therefore the timing paths through this arcs are not critical and the timing arcs from these pins can be safely disabled -- click both pins to set their //Path breaker// property. Now all the gates are highlighted <color lime>green</color> indicating that there is no more unbroken combinational cycles in the circuit:

{{ vme-tm-break_timing_arcs-complete.circuit.png?nolink |Breaking timing arcs in VME circuit}}

The information about disabled timing arcs can now be exported as a set of SDC constraints for subsequent use in the conventional EDA tools -- click on the ''Write SDC...'' button and save the constraints in ''vme-tm.circuit.sdc'' file, which will be as follows:

<file tcl vme-tm.circuit.sdc>
# Path break SDC file generated by Workcraft 3 (Return of the Hazard), version 3.2.4
set_disable_timing U1 -from AN -to ON
set_disable_timing U5 -from A2 -to ON
set_disable_timing U16 -from A1 -to ON
set_disable_timing U17 -from A2N -to ON
</file>

===== Insertion of testable buffers =====

Let us now use a different approach to loop breaking and insert testable buffers in every combinational cycle. For this, activate //Cycle analyser// {{:help:circuit:editor_tools-cycle_analysis.png?nolink|[Y] Cycle analyser}} tool and clear //Path breaker// properties from all the pins by pressing {{:help:circuit:tool_controls-loop_breaking-clear_all.png?nolink|Clear all path breaker pins}} button.

All the components and pins on a cycle are highlighted <color magenta>magenta</color>. The challenge is to eliminate all the cycles by setting //Path breaker// property of as few output pins as possible. You can try to do this manually by clicking the output pins to toggle their //Path breaker// property -- path breaker pins and components will turn <color orange>orange</color> and the ones that become not on a cycle turn <color lime>green</color>.

You can also rely on the //automatic// loop breaking: press {{:help:circuit:tool_controls-loop_breaking-tag_necessary.png?nolink|Auto-append path breaker pins as necessary to complete cycle breaking}} for eliminating all the remaining cycles or {{:help:circuit:tool_controls-loop_breaking-untag_redundant.png?nolink|Auto-discard path breaker pins that are redundant for cycle breaking}} for discarding redundant path breaker pins.

Interestingly, setting //Path breaker// property for the output pin of a single gate ''U17'' is sufficient to eliminate all the combinational cycles:

{{ vme-tm-break_self_loops.circuit.png?nolink |Breaking self-loops in VME bus controller}}

Now insert a testable buffer at the output of ''U17'' by pressing **Insetr TBUF/TINV** button:

{{ vme-tm-tbuf.circuit.png?nolink |Insertion of testable buffers in VME bus controller}}

Usually a custom SCAN insertion script is employed at this stage  for replacing ''TBUF'' and ''TINV'' gates by specialised SCAN-enabled components and arranging them into the SCAN chain. A basic alternative to such procedure is implemented in Workcraft. Pressing the **Insert SCAN** button automatically creates the SCAN chain  following a sequence of steps (the names of SCAN ports and pins can be changed in //Edit->Preferences...->Models->Digital Circuit// preferences):
  - Add SCAN ports ''<color red>scanck</color>'', ''<color red>scanen</color>'', ''<color red>scantm</color>'', ''<color red>scanin</color>'', and ''<color blue>scanout</color>''.
  - Convert ''TBUF'' and ''TINV'' components into their SCAN-enabled alternatives ''TBUF_SCAN'' and ''TINV_SCAN'', respectively, with additional ''<color red>CK</color>'', ''<color red>SE</color>'', and ''<color red>SI</color>'' pins.
  - Connect ''<color red>scanck</color>'', ''<color red>scanen</color>'' and ''<color red>scantm</color>'' ports to ''<color red>CK</color>'', ''<color red>SE</color>'' and ''<color red>TM</color>'' pins of testable components, respectively.
  - Arrange testable components in the SCAN chain between ''<color red>scanin</color>'' and ''<color blue>scanout</color>'' ports.

The final VME bus controller with SCAN should look as follows:

{{ vme-tm-scan.circuit.png?nolink |Insertion of SCAN in VME bus controller}}

Note that disabling timing arcs and generation of SDC file can be combined with insertion of testable elements if necessary.

===== Verification =====

Insertion of testable buffers and SCAN should not break the circuit. This can be verified in a usual way via //Verification// menu using the original STG as the environment for the modified circuit -- all the standard verification properties, namely //Conformation//, //Deadlock freeness//, and //Output persistency// should pass.

Note that the will be warnings about unused ''<color blue>scanout</color>'' output and about dead places associated with ''<color red>scanck</color>'', ''<color red>scanen</color>'', ''<color red>scantm</color>'', ''<color red>scanin</color>'' ports. Both warnings are expected and can be safely ignored. Indeed, the behaviour of SCAN output is not specified in the //mission-mode// STG, and all the SCAN input ports are intentionally forced low, i.e. their //Init to one// property is unset and their //Set function// is assigned to constant ''0''.

===== Solutions =====

Download all the Workcraft models discussed in this tutorial here:

<wrap download>{{loop_breaking.zip|Circuit models}}</wrap>

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