====== Design of WAIT2 component ======

Decompose the ''WAIT2'' component into ''WAIT'' for waiting the high level of non-persistent signal <color red>sig</color> and ''WAIT0'' for its low level. The control module ''W2C'' toggles between ''WAIT'' and ''WAIT0'' according to the polarity of its <color red>ctrl</color> input.

{{ WAIT2.circuit.svg?50% |Schematic of WAIT2 component}}

Behaviour of ''W2C'' is captured by the following STG.

{{ W2C.stg.svg?35% |STG of W2C control}}

Verify the STG for consistency, deadlocks, output-persistency and input-properness.

Note that this STG has CSC conflicts. Resolve them either automatically or manually, e.g. by concurrency reduction, as follows:

{{ W2C-cr.stg.svg?35% |STG of W2C control with concurrency reduction to resolve CSC conflicts}}

Proceed to synthesis and technology mapping with either //MPSat// or //Petrify// backend. The result should look similar to this:

{{ W2C-tm.circuit.svg?50% |Implementation of W2C control}}

Experiment with reset strategies using //Initialisation analyser// tool. One can notice that ''<color red>ctr</color>'' input is initially set to ''0'' by ''CYCLE'' module, also C-element ''U2'' can be explicitly reset. These lead to initialisation of ''<color blue>ctrl_1</color>'' and ''<color blue>ctrl_0</color>'' to ''0'', which reset ''<color red>san_1</color>'' and ''<color red>san_0</color>'' (outputs of ''WAIT'' and ''WAIT0'').