====== Advanced Design of Asynchronous Circuits ======

//11-12 July 2019 at [[http://www.dialog-semiconductor.com/|Dialog Semiconductor]], Germiring, Germany//

This course covers a variety of advanced topics, including logic decomposition and technology mapping for complex STGs, and also initialisation and testing of speed-independent circuits.
===== Day 1: Initialisation, loop breaking, hierarchy =====

  * Initialisation of speed-independent circuits
    * Lecture and demo (30 min) -- <wrap download>{{initialisation-slides.pdf|slides}}</wrap>, <wrap download>{{initialisation-examples.zip|examples}}</wrap>
    * Practical (1 hour) -- [[tutorial:method:initialisation:start|Initialisation of speed-independent circuits]]

  * Loop breaking and testing
    * Lecture and demo (30 min) -- <wrap download>{{loop_breaking-slides.pdf|slides}}</wrap>, <wrap download>{{loop_breaking-examples.zip|examples}}</wrap>
    * Practical (1 hour) -- [[tutorial:method:loop_breaking:start|Loop breaking and offline testing]]

  * N-way conformation
    * Lecture and demo (30 min) -- <wrap download>{{nway_conformation-slides.pdf|slides}}</wrap>
    * Practical (1 hour)  -- [[tutorial:method:hierarchical_design:start|Verification and synthesis of hierarchical designs]]

  * Support for hierarchical design in Workcraft
    * Vision on automation and reuse (30 min) -- <wrap download>{{hierarchy-slides.pdf|slides}}</wrap>
    * Demo of progress so far (30 min)

===== Day 2: Logic decomposition, technology mapping, timing conditions =====

  * Logic decomposition and Technology mapping
    * Lecture (1 hour) -- <wrap download>{{logic_decomposition-slides.pdf|slides}}</wrap>
    * Surgery of interesting STGs (1 hour)
    * Practical (1 hours) -- [[tutorial:method:technology_mapping:start|Logic decomposition and technology mapping]]

  * Design of interrupt handler (30 min) -- <wrap download>{{interrupt_handler-slides.pdf|slides}}</wrap>

  * Design with timing conditions (30 min) -- <wrap download>{{design_with_timing_conditions-slides.pdf|slides}}</wrap>

  * Demo of [[https://github.com/danilovesky/verimap|Verimap]] for converting single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks (30 min)

  * Private demos and discussions (2 hours)
<WRAP hide>
  * Timing verification with global constraints
    * Lecture (30 min) -- <wrap download>{{timing_verification-slides.pdf|slides}}</wrap>
    * Demo (30 min)  -- <wrap download>{{timing_verification-examples.pdf|slides}}</wrap>

  * Vision and discussion for functional verification using async-SVA (1 hour) -- <wrap download>{{functional_verification-slides.pdf|slides}}</wrap>
</WRAP>