<WRAP>
<carousel infinite=true&dots=true&autoplay=true>
  * {{ :overview:asymmetric_key_generator:screenshot.png?direct | }}
    [[:overview:asymmetric_key_generator:start|Modelling and verification of concurrent algorithms with Petri Nets]]

  * {{ :overview:instruction_decoder:screenshot.png?direct | }}
    [[:overview:instruction_decoder:start|Synthesis of instruction decoder using Conditional Partial Order Graphs]]

  * {{ :overview:vme_bus_controller:screenshot.png?direct | }}
    [[:overview:vme_bus_controller:start|Specification and synthesis of speed-independent controllers from Signal Transition Graphs]]

  * {{ :overview:baseband_transmitter:screenshot.png?direct | }}
    [[:overview:baseband_transmitter:start|Modelling self-timed pipelines using Dataflow Structures]]
</carousel>
</WRAP>