====== Instruction set synthesis using Conditional Partial Order Graphs ======

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<code | ARM M0 instruction classes>
 DR STRIMM = PCIU -> IFU + IFU -> ALU + ALU -> MAU + MAU -> PCIU_2 + PCIU_2 -> IFU_2
 RN TO PC = ALU -> IFU
 LDR STR PC = PCIU -> IFU + IFU -> ALU + ALU -> MAU + MAU -> IFU_2
 LDM = MAU -> IFU
 LDM STM = MAU + PCIU -> IFU
 RN TO RN = PCIU -> IFU + ALU
 STR LDRREG PUSH POP = PCIU -> IFU + ALU -> MAU LDR = ALU -> MAU + MAU -> IFU
 COND BRANCH = PCIU -> PCIU_2 + PCIU_2 -> IFU
 #123 TO PC BRANCH BL BLX = PCIU -> IFU + IFU -> ALU + ALU -> IFU_2
 #123 TO RN = PCIU -> IFU + IFU -> ( PCIU_2 + ALU ) + PCIU_2 -> IFU_2 + ALU -> IFU_2
</code>

  * <wrap download>{{arm_m0-instruction_classes.cpog.work}}</wrap>
  * <wrap download>{{arm_m0-instruction_composition_compact.cpog.work}}</wrap>
  * <wrap download>{{arm_m0-instruction_composition.cpog.work}}</wrap>