===== Cycle analyser =====

Combinational cycles are common in asynchronous circuits -- they (along with latches) usually implement "memory" of the circuit. Verilog netlist for such cyclic circuits, however, may upset conventional EDA tools for timing analysis (e.g. Synopsys PrimeTime) and offline testing (e.g. Synopsys TetraMAX):

  * Static timing analysis requires the circuit to be free of combinational cycles and breaks them by disabling some of the timing arcs. The choice of the timing arcs to disable, however, is often difficult to predict and suboptimal, and in particular may cause removal of timing paths that are important for timing analysis, e.g. critical paths.

  * Offline testing may also be affected by the combinational cycles as they limit the //controlability// of the circuit -- the ability to set every signal to a specific state via the circuit's primary inputs.

Workcraft introduces a //Path breaker// property for the component pins to explicitly break the combinational cycles. Interpretation of this property differs for the input and output pins of a gate:

  * For each **input pin** whose //Path breaker// property is set, a ''set_disable_timing'' constraint is generated -- it disables the timing arcs from that input pin, thus removing timing paths through the pin. These constraints can be dumped into an SDC file and subsequently used to explicitly instruct a timing analysis tool to disable specific timing arcs, rather than rely on its unpredictable arc selection algorithm. Careful selection of the timing arcs for disabling may help to break all the combinational cycles in the circuit while preserving the important/interesting timing paths. This requires creativity from the designer and is not always possible.

  * For each **output pin** whose //Path breaker// property is set, a special element called //testable buffer// or //testable inverter// is inserted. Such testable elements need to be designed and characterised for each gate library, so the timing analysis tool is aware of their path breaking capability. Moreover, the testable elements can be further extended with SCAN features, making asynchronous design compatible with conventional DfT methodology\ [(Lloyd_2014_SNUG)].

Note that both ways of dealing with combinational cycles can be combined in the same circuit. 

//Cycle analyser// {{:help:circuit:editor_tools-cycle_analysis.png?nolink|[Y] Cycle analyser}} tool provides a convenient GUI for exploration of loop breaking alternatives. It automates the removal of combinational cycles and the insertion of testing features in asynchronous circuits. //Cycle analyser// control panel looks as follows:

{{ tool_controls-loop_breaking.png?nolink |}}

When the tool is activated, the circuit gates are highlighted using the following scheme (the colours can be adjusted in the preferences of digital circuit model -- see //Edit->Preferences...->Decoration->Analysis//):
  * Zero delay gates and their output pins are highlighted <color grey> grey</color>. This is to indicate that zero delay gates cannot be delayed by inserting testable buffers. Input pins of zero delay gates can still be set as path breakers though.
  * Components and pins that lay on a cycle are highlighted <color magenta> magenta</color>.
  * Pins whose //Path breaker// property is set are highlighted <color orange>orange</color>. Components with path breaker pins are also highlighted <color orange>orange</color>.
  * Components and pins that do not belong to any cycle are highlighted <color lime>green</color>.

//Path breakers// table enumerates the pins whose //Path breaker// property is set. Note that //Path breaker// property of a pin can be toggled while in //Cycle analyser// tool by clicking the corresponding pin; clicking on a gate toggles //Path breaker// property of its only output. The change is immediately visualised via updated highlighting of components and pins. This enables convenient exploration of possible cycle breaking strategies.

//Cycle analyser// also provides several ways of changing //Path breaker// property for a group of output pins (input pins are not affected by these actions):

  * {{:help:circuit:tool_controls-loop_breaking-self_loop.png?nolink|Path breaker all self loops}} - Tag //Path breaker// property for output pins of components with feedback loops. Note that feedback loops via zero-delay inverters or buffers are also included.
  * {{:help:circuit:tool_controls-loop_breaking-tag_necessary.png?nolink|Auto-append path breaker pins as necessary to complete cycle breaking}} - Set //Path breaker// property of output pins as necessary to break all the cycles in the circuit.
  * {{:help:circuit:tool_controls-loop_breaking-untag_redundant.png?nolink|Auto-discard path breaker pins that are redundant for cycle breaking}} - Clear //Path breaker// property of output pins that are redundant for breaking all cycles in the circuit.
  * {{:help:circuit:tool_controls-loop_breaking-clear_all.png?nolink|Clear all path breaker pins}} - Clear //Path breaker// property for all the pins.

Once all the cycles are broken by strategically assigning the //Path breaker// property to the pins, the buttons at the bottom of the tool panel are used as follows:

  * **Insert TBUF/TINV**  -- insert testable buffers/inverters after output pins with //Path breaker// property set. Note that insertion of testable buffers is optimised as follows: If the path breaker pin belongs to a buffer (inverter), or if the only gate it drives is a buffer (inverter), then, instead of inserting a new testable gate, that buffer (inverter) is converted into the testable buffer(testable inverter).

<WRAP info round center 90%>
By default the testable buffer gate is ''TBUF'' with input ''I'' and output ''O''; testable inverter gate is ''TINV'' with ''I'' and ''ON'' pins. These names can be changed in //Edit->Preferences...->Models->Digital Circuit// preferences via //Testable buffer name and input-output pins// and //Testable inverter name and input-output pins// settings.
</WRAP>

  * **Insert SCAN** -- insert SCAN ports and connect them to the //testable buffers//.

<WRAP info round center 90%>
When connecting a gate to scan ports its module name is automatically changed by adding ''_SCAN'' suffix. This default suffix can be changed in //Edit->Preferences...->Models->Digital Circuit// preferences via //Scan module suffix// setting. By default SCAN primary inputs are called ''scanck'', ''scanen'', ''scanin'', and ''scanout'' while the corresponding pins of testable gates are ''CK'', ''SE'', ''SI'', and ''SO'' (the latter is only used in multi-output components). These names can also be changed in //Edit->Preferences...->Models->Digital Circuit// preferences via //Scan clock port / pin names//, //Scan enable port / pin names//, //Scan input port / pin names// and //Scan output poert / pin (for multi-output component) names// settings.
</WRAP>

  * **Write SDC...** -- write out an SDC file with ''set_disable_timing'' constraints for each input pin with //Path breaker// property set. This button is disabled if there are no input pins with //Path breaker// property set.

<WRAP info round center 90%>
By default the produced SDC file uses the names of gates and pins as they are defined in the //Property editor// for the corresponding nodes. If necessary, these names can be substituted by providing a conversion file in //Edit->Preferences...->Models->Digital Circuit// preferences via //Substitution rules for export// setting. For example, ''libraries/workcraft-tsmc_ghp.cnv'' file has rules to convert ''libraries/workcraft.lib'' gates to match the naming convention of TSMC GHP library. This is a convenient way to convert a circuit (and its constraints) mapped into one gate library to be used with another library.
</WRAP> 


[(Lloyd_2014_SNUG> D.\ Lloyd, R.\ Illman: //"Scan insertion and ATPG for C-gate based
asynchronous designs"//, in Synopsys User Group (SNUG), 2014.)]