===== Initialisation analyser =====

Initialisation (or reset) of a speed-independent circuit is an important part of the design process because a circuit can malfunction if its initial state is incorrect. Note that the initialisation phase of a speed-independent circuit does not have to be speed-independent: It is assumed that there is a special ''<color red>reset</color>'' signal that is generated externally and behaves as follows:
  * When the power is connected, ''<color red>reset</color>'' is low.
  * It stays low for sufficiently long time to complete the initialisation of all gates.
  * Eventually ''<color red>reset</color>'' goes high, at which point the circuit is already correctly initialised and the normal speed-independent operation begins.
  * ''<color red>reset</color>'' stays high for the whole time of circuit normal operation. 

There are several ways of circuit initialisation that can be used in combination:
  * Rely on the initial state of some of the inputs (which are guaranteed to be correctly initialised by the environment). They propagate through some of the logic gates to initialise some of the internal and output signals.
  * Substitute some of the gates with ones containing an extra input that can act as a set or reset pin.
  * Insert additional gates to explicitly initialise the internal and output signals. Such gates will act as buffers during the normal operation, so one has to be careful not to break any //isochronic forks//.

//Initialisation analyser// {{help:circuit:editor_tools-initialisation_analysis.png?nolink|[I] Initialisation analyser}} tool is designed to aid the decision of how to reset a speed-independent circuit. The tool uses //Init to one// and //Forced init// properties of circuit signals (i.e. primary input ports and output pins of circuit components):
  * //Init to one// property defines the initial state of the signal. If a circuit is synthesised by one of the backend tools, then the initial state of all its signals is set automatically. However, if the circuit is manually altered, then the designer is responsible for specifying the initial states of the signals.
  * //Forced init// property defines if the signal is known to be in a correct initial state. For a primary input it means the environment takes care of initialising the signal to its expected state.  For a  component output pin it means that the necessary circuitry will be added to properly initialise that pin.

These properties can be viewed and modified in the //Property editor// when an input port or an output pin is selected. Note that selecting a single-output component (i.e. a gate) also reveals these properties of its only output pin. Note that //zero delay// gates hide //Force init// property as these gates should not be modified.

//Initialisation analyser// uses these properties as follows. It considers the signals whose //Forced init// property is set as //initialised//, while the remaining signals are assumed as //uninitialised//. The tool tries to evaluate each //uninitialised// signal on the //Init to one// property of //initialised// signals. If the Boolean value of a signal can be derived, then it is said to have //propagated initial state// and the signal is also considered //initialised//. The tool repeats evaluation of //uninitialised// signals until no further progress can be made, i.e. no new //initialised// signals can be obtained. At this stage, if some signals are still //uninitialised// it means //Forced init// property of the circuit signals needs to be adjusted, until all the signals are successfully initialised.

Sometimes the correct initial state of a signal cannot be achieved and the signal is said to have //initialisation problem//. There are two sources of initialisation problems:
  * //Conflict of initialisation//, which happens when the propagated initial state of a signal does not match its //Init to one// property. This often indicates a mistake, e.g. incorrect initial value of the signal, however, there are legitimate situations where such conflicts can occur.
  * //Unreachable initial state//, which happens with sequential (self-dependent) signals whose expected initial state cannot be reached by assigning the component inputs.

In both cases such a problematic signal needs to be explicitly initialised by setting its //Forced init// property.

//Initialisation analyser// visualises the initialisation state using the //Gate highlight legend// shown in the //Tool controls//:

{{ tool_controls-initialisation.png?nolink |}}

By default the highlighting scheme for circuit components is as follows (the colours can be adjusted in the preferences of digital circuit model -- see //Edit->Preferences...->Decoration->Analysis//):
  * Components whose initial state cannot be determined via propagation of //forced// signals are not highlighted (i.e. remain white).
  * Zero delay components, which must not be modified by reset insertion, are highlighted <color grey> grey</color>.
  * Components with initialisation problems (conflict of initialisation or unreachable initial state) are highlighted <color magenta> magenta</color>.
  * Components whose pins have //Forced init// property set are highlighted <color orange>orange</color>.
  * Correctly initialised components are highlighted <color lime>green</color>.

The pins and ports are coloured according to their initialisation state (<color red>red</color> for high level and <color blue>blue</color> for low level), as follows:
  * The pin outline color indicates the //expected// initialisation state defined by the //Init to one// property, while its background color reflects the actual //propagated// initialisation state. In case of a mismatch (the propagated value differs from the expected one) the problematic pin can be easily identified by its different outline and background colours.
  * Output pins whose //Forced init// property is set are visualised by diamond shape. The initial state of such pins is forced to the //expected// value, according to their //Init to one// property.

The color scheme for wires is as follows:
  * Wires of //uninitialised// signals are coloured black.
  * Wires of //initialised// signals are coloured <color red>red</color> or <color blue>blue</color> according to their initial state.

//Force init pins// table enumerates the pins whose //Forced init// property is set. Note that //Forced init// property of a signal can be toggled while in //Initialisation analyser// tool by clicking the corresponding input port, output pin, or a gate. This enables convenient exploration of possible reset strategies. The tool also provides several ways of changing //Force init// property for a group of contacts:

  * {{tool_controls-initialisation-input_port.png?nolink|Force init all input ports (environment responsibility)}} - Tag //Forced init// property for all input ports. Note that it is the environment responsibility to guarantee the correct initialisation of primary inputs whose //Forced init// property is set.
  * {{tool_controls-initialisation-problematic.png?nolink|Force init output pins with problematic initial state}} - Tag //Forced init// property for all output pins with problematic initial state.
  * {{tool_controls-initialisation-sequential.png?nolink|Force init output pins of sequential gates}} - Tag //Forced init// property for output pins of all sequential gates.
  * {{tool_controls-initialisation-tag_necessary.png?nolink|Auto-append force init pins as necessary to complete initialisation}} - Set //Forced init// property of output pins as necessary to complete initialisation of the circuit.
  * {{tool_controls-initialisation-untag_redundant.png?nolink|Auto-discard force init pins that are redundant for initialisation}} - Clear //Forced init// property of output pins that are redundant for the circuit initialisation.
  * {{tool_controls-initialisation-clear_all.png?nolink|Clear all force init ports and pins}} - Clear //Forced init// property for all input ports and output pins.

Circuit initialisation comprises three steps:

  - **Reset exploration** -- Decide which signals should be forced to the initial state, so that the correct initial values propagate to the remaining circuit components. Selecting a good set of forced signals is a creative process with multiple optimisation targets (avoiding critical paths, circuit size, gate complexity, etc.) and relies on designer experience.
  - **Reset insertion** -- Insert the reset port ''<color red>reset</color>'', set its //Init to one// property according to the reset active state (//false// for active low, //true// for active high), and use it to initialise all the signals that have //Force init// property set.
  - **Reset validation**  -- Clear //Force init// property of all component pins and input ports, set //Force init// property for the reset port, and check that all the circuit components are correctly initialised.