===== Workcraft v3.1.1 (2016-06-30) =====

=== Usability improvements ===
  * Tool-specific mouse cursors are used to emphasise the currently active tool.
  * Conversion of work files to supported export formats from command line.
  * Correctly enable/disable menus on switching between works.
  * Initial support for checking SVA-like invariants in circuits and STG models.
  * In OSX shortcuts are based on <key>Command</key> key instead of <key>Ctrl</key>.
  * Native OSX menu bar for Mac users.
  * Both <key>Delete</key> and <key>Backspace</key> keys can be used for removing selected objects (for laptops without <key>Delete</key> button).
  * Alignment of multi-line labels.
  * Rendering of check-boxes, radio-buttons and file selection dialog icons for high-DPI displays.

=== Model and tool plugins ===
  * Digital Circuit plugin
    * //Custom property... [MPSat]// and //Custom assertion... [MPSat]// items are added to //Verification// menu for checking Reach predicates and SVA-like invariants on circuits.
    * Transformation tool for detaching joints from circuit driver pins (forks on output contacts and input ports).
    * Analysis tool for identifying and breaking combinational loops in one of two ways:
      * Insert specially designed loop-breaking gates, e.g. C-elements implemented as proper sequential gate.
      * Tag input pins of gates as path breakers -- these subsequently can be exported as ''set_disable_timing'' SDC constraints.


  * Signal Transition Graph plugin
    * SVA-like invariants can be checked via //Verification->Custom assertion... [MPSat]// menu.

  * Conditional Partial Order Graph plugin
    * Synthesis into Digital Circuit via Verilog import.
    * Allow self-loops in Directed Graph and CPOG models.
    * Update of conditions when CPOG variables change.
    * Prevent ''pgminer'' from running on empty graph.

=== Fixes and technical stuff ===
  * Reduce the probability of concurrent modification exception (was often seen on import from Verilog).
  * Bug-fixes in renaming STG transitions.
  * Updated UnfoldingTools to support SVA-like invariants.
  * Updated ScEnco backend tool to support Verilog output.
  * Prevent creation of ''~/felxdock/'' directory.