// Verilog netlist generated by Workcraft 3 (Return of the Hazard), version 3.2.3 module CYCLE (chrg_ack, chrg_req, uv_ctrl, uv_san, reset); input chrg_ack, uv_san, reset; output chrg_req, uv_ctrl; wire me_r1_rst_ON, me_r2_rst_ON; NAND2 me_r1_rst (.ON(me_r1_rst_ON), .A(uv_san), .B(reset)); NOR2B me_r2_rst (.ON(me_r2_rst_ON), .AN(reset), .B(chrg_ack)); MUTEX me (.r1(me_r1_rst_ON), .g1(uv_ctrl), .r2(me_r2_rst_ON), .g2(chrg_req)); // signal values at the initial state: // me_r1_rst_ON !me_r2_rst_ON uv_ctrl !chrg_req !chrg_ack !uv_san !reset endmodule